Question 1: Write a Verilog code to swap the contents of two registers with and without a temporary register.
// With temporary register
module SwapWithTemp (
input reg [7:0] a,
input reg [7:0] b,
output reg [7:0] a_swapped,
output reg [7:0] b_swapped
);
reg [7:0] temp;
always @* begin
temp = a;
a_swapped = b;
b_swapped = temp;
end
endmodule
//testbench
module testbench;
reg [7:0] a, b;
reg [7:0] a_swapped_temp, b_swapped_temp;
// Instantiate modules
SwapWithTemp uut_temp (.a(a), .b(b), .a_swapped(a_swapped_temp), .b_swapped(b_swapped_temp));
initial begin
// Initialize input values
a = 10;
b = 20;
// Display initial values
$display("Initial values: a=%d, b=%d", a, b);
// Simulate with temporary register
#1; // Delay for one simulation time unit
$display("With temporary register: a_swapped=%d, b_swapped=%d", a_swapped_temp, b_swapped_temp);
end
endmodule
Output:
Initial values: a= 10, b= 20
With temporary register: a_swapped= 20, b_swapped= 10
V C S S i m u l a t i o n R e p o r t
module SwapWithoutTemp (
input reg [7:0] a,
input reg [7:0] b,
output reg [7:0] a_swapped,
output reg [7:0] b_swapped
);
always @* begin
a_swapped <= b;
b_swapped <= a;
end
endmodule
//testbench
module testbench;
reg [7:0] a, b;
reg [7:0] a_swapped_no_temp, b_swapped_no_temp;
// Instantiate module
SwapWithoutTemp uut_no_temp (.a(a), .b(b), .a_swapped(a_swapped_no_temp), .b_swapped(b_swapped_no_temp));
initial begin
// Initialize input values
a = 10;
b = 20;
// Display initial values
$display("Initial values: a=%d, b=%d", a, b);
// Simulate without temporary register using non-blocking assignments
#1; // Delay for one simulation time unit
$display("Without temporary register: a_swapped=%d, b_swapped=%d", a_swapped_no_temp, b_swapped_no_temp);
// End simulation
$stop;
end
endmodule
Output:
Initial values: a= 10, b= 20
Without temporary register: a_swapped= 20, b_swapped= 10
V C S S i m u l a t i o n R e p o r t
Question 2: What is the difference between wire and reg data types?
wire is used for connecting different hardware elements that are driven by continuous assignments while reg is used as data storage, it can hold values between assignments and is typically used for sequential logic.
wire is used for combinational logic and does not store any state while reg is used for variables in procedural blocks, we can not drive or assign reg data type variables with assign assignment.
Question 3: Can wire be used in always block?
wire cannot be used directly in an always block. The wire type is specifically designed for continuous assignments using the assign statement and is meant for connecting different components in a module.
always blocks are generally used with the reg type for sequential and procedural logic. If you need a signal in an always block, it is more appropriate to use a reg or another appropriate data type for the specific logic you are implementing.
Question 4: Write the default value of integer, real, reg, time, wire.
Write the default value of integer, real, reg, time, wire.
Integer = x
Real = 0
Reg = x (reg is used for storage so default value will be x i.e no value stored)
Time = x
Wize =z(wire is used for connected the elements so default value will be z)
Question 5: What is the procedural block?
a procedural block refers to a block of code that specifies procedural assignments and executes sequentially based on certain events or conditions. Procedural blocks include always blocks and initial blocks.
Question 6: Write a Verilog code for counter which counts 0-5.
module Counter (
output reg [2:0] count,
input clk,
input rst
);
always @ (posedge clk or posedge rst) begin
if (rst)
count <= 3'b0;
else if (count == 3'b101)
count <= 3'b0;
else
count <= count + 1;
end
endmodule
Question 7: What is the difference between always and initial statements?
always is used for describing sequential and combinational logic, and it continuously executes based on certain events (e.g., edge-triggered).
initial is used for specifying initial conditions and is executed only once at the beginning of simulation.
Question 8: Define types of Delay in Verilog.
# Delay:
· The # delay is a time-based delay used to introduce a time delay in simulation.
· It specifies the number of simulation time units for which the simulation should be paused before executing the next statement.
Example:
initial begin
// Code before delay
#10; // Delay of 10 time units
// Code after delay
end
Question -9 What is the difference between blocking & non-blocking assignments?
Blocking (=): The statements in the sequential block are executed in a sequential order, and the next statement waits for the completion of the previous one.
Non-blocking (<=): All statements in the block execute concurrently, and the order of execution does not affect the order of assignment.
Question 10. How many initial blocks can a module have? How will it be executed?
A module can have multiple initial blocks. They will be executed in the order in which they are defined. The execution of initial blocks is concurrent, and the order of execution is determined by the simulator’s scheduling algorithm based on sensitivity lists and delays specified in each initial block.