Operators are symbols or characters that can perform different operations on operands. These operands may be variables, constants, or expressions. operators are used to perform various operations on signals or variables. These operators can be broadly classified into several categories based on their functionality. The Verilog operators are similar to the operators used in C programming to provide results based on an operation. Verilog offers a wide range of operators for tasks such as arithmetic, logical operations, bitwise manipulation, comparisons, and more. Here are some of the common operator types in Verilog:
Arithmetic Operators:
An arithmetic operation is carried out by the arithmetic operator on two operands. The outcome of a division or modulus operator is x if the second operand is zero. The power operator’s results will be real if either of its operands is true. If the second operand of a power operator is 0, the result will be 1.
+ Addition
- Subtraction
* Multiplication
/ Division
% Modulus produces the remainder
** Power
Bitwise Operators:
Bitwise operations are performed bit by bit. To calculate a single-bit result, this operator will combine a bit from one operand with its matching bit from the other operand. When vectors are different sizes, the MSBs for the smaller vectors are treated as zeros.
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
~^ or ^~ Bitwise XNOR
~ Bitwise NOT
Logical operators:
Logical operators always produce a single bit of output i.e 0 , 1, x.
1(true), 0(false), x(unknown)
Any non-zero is counted as logic true, even if the number is negative or positive. When both of the operands of a logical and (&&) are true or non-zero, the result is 1 or true. When both of the operands of a logical and (||) are true or non-zero, the result is 1 or true. X will also be the result if any of the operands is x. A non-zero or true operand will become 0 and a zero or false operand will become 1, but an x will stay an x when using the logical negation(!) operator.
&& Logical AND
|| Logical OR
! Logical NOT
Shift Operators:
Operators on the shift don’t wrap around. Shift operators are two types.
<< and >> Logical shift operators
<<< and >>> Arithmetic shift operators
Logical shift:
Logical shift operators shift empty bit positions in a vector with zeros and shift it to the left or right by a specified number of bits.
<< Left shift
>> Right shift
Arithmetic shift:
Arithmetic shift operators shift a vector to the left or right by a certain amount of bits and, if an expression is signed, fill empty bit locations with sign bits; otherwise, they fill them with zeros.
<<< Arithmetic left shift
>>> Arithmetic right shift
Relational Operators:
The relational operation takes out on two operands, returning 1 if the expression is true and 0 if it is false. The outcome will be x if any of the operands is x or z.
Equality Operators:
== Equal to
!= Not equal to
> Greater than
< Less than
>= Greater than or equal to
<= Less than or equal to
== Equality, result may be unknown
!= Inequality, result may be unknown
=== case equality, result will be 1 0r 0
!== case inequality, result will be 1 or 0
The equality and inequality operators compare two operands bit by bit and return 1 or 0 if the comparison is either true or false. If either operand has bits set to x or z, they will return value as ‘x’.
The case equality and case inequality compare two operands bit by bit—even for the x and z bits—and return 1 or 0, respectively, whether the comparison is correct or incorrect. They conduct a precise bit-by-bit comparison. The result will be 0 (false) if any of the bits are not matched.
Conditional Operator:
Both assign and procedural blocks allow the use of conditional operators.
While we choose conditional operators over if_else, if-else can only be used inside procedural blocks.
Ternary operators are also mentioned to as conditional operators. it returns one of two values depending on a condition.
condition ? true_value : false_value
Example:
2×1 mux
Output of mux Y= select? a:b // if select is true , output Y= a , else Y=b
?: Ternary conditional operator (Conditional Assignment)
Concatenation Operator:
{} It is used to concatenate values to form larger vectors or arrays.
{op1,op2,..} : concatenates op1, op2,… to single output vector.
Operands must be known sizes; otherwise, they will be considered default sizes.
Replication Operator:
Based on a parameter, a replication operator can be employed to generate a vector with the necessary 1s and 0s.
Replication and concatenation operators can be combined.
Example:
{n{}} Replicates a signal ‘n’ times to create a larger vector.
Reduction Operators:
By applying a bitwise operation on a single vector operand, reduction operators produce output in units of 1 bit.
Reduction operators work bit by bit from right to left.
The outcomes of reduction nand, reduction nor, and reduction xnor are the reversed equivalents of the outcomes of reduction and, reduction or, and reduction xor.
& Bitwise AND reduction
| Bitwise OR reduction
^ Bitwise XOR reduction
~& NAND reduction
~| NOR reduction
~^ XNOR reduction
Assignment Operators:
= Blocking assignment
<= Non-blocking assignment
In Verilog, these operators can be used to carry out a variety of operations inside procedural blocks (always, initial, task, or function), as well as continuous assignments (assign statements). For efficient Verilog code to be written to represent hardware behaviour, it is essential to understand and correctly use these operators.