Packed Array:
1. A packed array is similar to a vector in verilog, and it stores data in a single memory address location for the entire array.
2. The dimensions of a packed array are declared before the array name, just like in the case of vectors.
3. Packed arrays support all SystemVerilog operations because they represent singular data variables, and their data is stored in a single memory address location. This feature makes them versatile for various programming tasks, especially when dealing with contiguous memory blocks.
4. Typically, packed arrays use limited data types such as `bit`, `reg`, or `logic`, reflecting their utility in storing binary or logical values in a single address location.
Packed arrays are contiguous blocks of memory.
Example:
module Packed_myArray;
reg [7:0] packed_array[3:0]; // Packed array of 8-bit registers with four elements
initial begin
// Initialize the packed array elements
packed_array[0] = 8'b01010101;
packed_array[1] = 8'b11001100;
packed_array[2] = 8'b00110011;
packed_array[3] = 8'b11110000;
// Access and display individual elements
$display("Element 0=%h", packed_array[0]);
$display("Element 1= %h", packed_array[1]);
$display("Element 2= %h", packed_array[2]);
$display("Element 3= %h", packed_array[3]);
end
endmodule
Output:
# vsim -voptargs=+acc=npr
# run -all
# Element 0=55
# Element 1= cc
# Element 2= 33
# Element 3= f0
# exit
# End time: 09:19:44 on Nov 04,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0In this example:
· We declare a packed array `packed_array` consisting of four 8-bit registers.
· The elements of the packed array are initialized with binary values.
· We then access and display the individual elements of the packed array. Each element holds an 8-bit binary value.
This code demonstrates the usage of a packed array in SystemVerilog to store and manipulate data with a contiguous memory layout.