Unpacked Array:
An unpacked array shares many similarities with arrays in Verilog.
Memory is allocated into multiple address locations, with the number of locations determined by the size of the array.
Each location within the array holds data of the same data type as defined during the declaration.
The dimensions of the array are declared after the variable name.
bit [7:0] my_array[3:0];
No restriction on data type, you can use any SystemVerilog data types
Unpacked arrays do not support all SystemVerilog operators because they represent multiple address locations rather than singular variables.
Packed arrays are non-contiguous blocks of memory.
Example:
module top;
int arr1[5];
int arr2[5];
integer i;
initial begin
for(i=0;i<5;i++) begin
arr1[i] = $urandom_range(50,100);
end
$display("arr1=%p",arr1);
for(i=0;i<5;i++) begin
arr2[i] = $urandom_range(10,20);
end
$display("arr2=%p",arr2);
//Copy 1st Array to 2nd Array
//for(i=0;i<5;i++) begin
// arr1[i] = arr[i];
// $display("arr1[%0d]=%0d",i,arr1[i]);
// end
//Copy 2st Array to 1nd Array
for(i=0;i<5;i++) begin
arr1[i] = arr2[i];
$display("arr1[%0d]=%0d",i,arr1[i]);
end
end
endmodule
Output:
# vsim -voptargs=+acc=npr
# run -all
# arr1='{59, 87, 99, 67, 96}
# arr2='{19, 13, 20, 16, 13}
# arr1[0]=19
# arr1[1]=13
# arr1[2]=20
# arr1[3]=16
# arr1[4]=13
# exit
# End time: 10:51:19 on Nov 04,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0